1. Field of the Invention
The present invention relates to an analog-to-digital converter (ADC), and more particularly, to a pipelined ADC, and a method of analog-to-digital conversion.
2. Description of the Related Art
In general, a pipelined analog-to-digital converter (ADC) is a multi-step quantizer, in which a plurality of ADCs are cascade-coupled with one another, and in which each of the ADCs has a relatively low resolution and the same or similar configurations with one another.
FIG. 1 is a block diagram illustrating a conventional pipelined ADC. Referring to FIG. 1, a conventional pipelined ADC 100 includes a plurality of n stages STG1 through STGn. Each stage STGi includes a sample-and-hold (S/H) circuit 110, an ADC 120, a digital-to-analog converter (DAC) 130, a subtractor 140, a residue amplifier 150 and a reference voltage driver 200. The S/H circuit 110 samples an analog input signal. The ADC 120 converts the analog input signal to a digital code having a low resolution. The DAC 130 and the subtractor 140 obtain a difference between the analog input signal and an analog signal corresponding to the digital code of the ADC 120. The residue amplifier 150 has a gain of 2Bi-1. Bi denotes a resolution of the stage STG1, and Bi is generally designed as ½ for correcting ADC errors generated in each of the stages, and referred to as a digital correction logic (DCL).
A building block including the S/H circuit 110, the DAC 130, and the residue amplifier 150 is referred to as a multiplying DAC (MDAC) 160. The MDAC is an essential block for the pipelined ADC.
A precise reference voltage is required for driving capacitors in each of the stages so that the MDAC 160 and the ADC 120 operate precisely. A unity-feedback buffer is used for obtaining the precise reference voltage.
FIG. 2 is a circuit diagram illustrating a reference voltage driver 200 employing a unity-feedback buffer for using the precise reference voltage.
Referring to FIG. 2, a reference voltage driver 200 includes a plurality of unity-feedback buffers 211, 213 and 215, a plurality of metal-oxide semiconductor (MOS) amplifiers 221, 223, and 225, a plurality of resistors R1, R2 and R3, and capacitors Cdcpl. The reference voltage driver 200 is connected externally via the capacitors Cdcpl for preventing fluctuation of the reference voltage so that the reference voltage is stably provided.
The stability of the reference voltage directly affects the performance of the pipelined ADC 100, and thus the reference voltage is required to be recovered at every analog-to-digital converting cycle. Therefore, the reference voltage driver 200 occupies a large size and consumes a lot of power, because the driving capacity and bandwidth of the unity-feedback buffers 211, 213 and 215 have to be sufficiently increased. In addition, the reference voltage of the reference voltage driver 200 cannot be modified or is required to be modified externally when the power supply voltage is required to be modified, and thus the reference voltage driver 200 has certain limitations when attempting to use a full dynamic range without using an external controller.